The present invention generally relates to a semiconductor device and a method of manufacturing same, and in particular to a miniaturized semiconductor device and a method of manufacturing same.
In recent years, various CPS (Chip Size Package) type semiconductor devices have been proposed. These semiconductor devices of CPS type have been viewed with interest for miniaturization virtually to a chip size.
As illustrated in FIG. 12, a CSP type semiconductor device adopts a frame 101 made of resin such as polyimide having formed thereon wiring patterns. On this frame 101, a die-attaching material 102 is applied, for mounting thereon a semiconductor chip 103.
Then, after curing the die-attaching material 102 by heating, the wiring patterns (not shown) formed on the resin frame 101 and electrode pads 105 formed on the semiconductor chip 103 are electrically connected.
Next, the semiconductor chip 103 is sealed with resin sealer 106 by means of transfer molding, and an outer-curing is performed to cure the resin sealer 106. Then, after placing the resulting molded article upside down, solder balls are placed on the resin frame 101 to be subjected to reflow melting in a reflow furnace, thereby forming external electrodes 107 for receiving and outputting electric signals from and to externally connected sections. Further, the resin frame 101 is cut into semiconductor devices. In FIG. 12, a reference numeral 108 indicates an insulating film.
According to the forgoing structure, the metal wires 104 are provided outside the semiconductor chip 103, and therefore the semiconductor device needs to be larger than the size of the semiconductor chip 103.
In the foregoing conventional structure, since metal wires are arranged on the periphery of the semiconductor chip, it is not possible to miniaturize the semiconductor device to the semiconductor chip size.
In response, Japanese Unexamined Patent Publication No. 223688/1998 (Tokukaihei 10-223688 published on Aug. 21, 1998) discloses a semiconductor device of a miniaturized package to the size of a semiconductor chip. As illustrated in FIG. 13, the semiconductor device disclosed in this publication is prepared by bonding an insulating substrate 116 made of polyimide and the like, having formed thereon electrically conductive patterns 115 (interposer), onto a semiconductor chip 111 using an elastic bonding agent 117. For the elastic bonding agent 117, epoxy bonding agent is adopted. The above publication also discloses, as one example, a semiconductor wherein the semiconductor chip 111 and the electrically conductive patterns 115 are connected by wire-bonding.
The electrically conductive patterns 115 formed on the insulating substrate 116 serve as an interposer, and signals outputted from the semiconductor chip 111 are sent to external connection terminals via the electrically conductive patterns 115. The external connection terminals are formed on one end of the electrically conductive patterns 115. The electrically conductive patterns 115 are formed so as to have a width within the range of from 50 to 100 xcexcm, and a thickness within the range of from 20 to 50 xcexcm. In FIG. 13, a reference numeral 112 indicates an electrode of the semiconductor chip 111. A reference numeral 113 indicates wires for use in electrically connecting the semiconductor chip 111 and the electrically conductive patterns 115 by wire-bonding. A reference numeral 114 indicates an insulating film.
However, the foregoing interposer in the conventional semiconductor device as disclosed in the above publication has the following disadvantages in its manufacturing process and reliability.
{circle around (1)} In order to attain a higher productivity, an insulating substrate made of, for example, polyimide, etc., may be bonded onto a semiconductor chip in the wafer state. In this case, however, a problem arises in that the wafer as bonded greatly warps, which leads to troubles in the subsequent transport process (for example, the manufacturing device stops operating, etc.,) or the wafer cracks, etc.
In the case of adopting the insulating substrate made of polyimide, it is possible to prevent the aforementioned warpage of the wafer by forming a slit of around 50 to 100 xcexcm by etching. However, by doing so, it becomes difficult to bond the insulating substrate onto the semiconductor chip.
{circle around (2)} Wires are generally formed on the insulating substrate made of polyimide by the following method. That is, first, a copper foil which has being rolled to have a thickness of 18 xcexcm is laminated onto the insulating substrate to be affixed thereto using a bonding agent, and it is then patterned to be a shape as desired by the wet-etching. Therefore, when adopting the foregoing method, the finest possible patterning would be a patterning having land and groove widths of 20 xcexcm, and therefore, the foregoing method is not suited for the formation of any finer wiring patterns.
{circle around (3)} As it is not possible to form elements, the foregoing method is not suited for multi-chip semiconductor device.
{circle around (4)} Due to a great difference in the linear thermal expansion coefficients between the insulating substrate made of polyimide, glass containing epoxy resin, etc., and the semiconductor chip, a heating cycle is liable to be damaged.
{circle around (5)} Epoxy, polyimide, etc., generally used as a material for the insulating substrate, absorbs water, and this leads to a poorer moisture-proofness of the semiconductor chip, or heat generated when mounting the substrate may cause the semiconductor chip separate from the insulating substrate.
{circle around (6)} The substrate made of polyimide, glass-containing epoxy resin, etc., is not light-shielding, and therefore an operation error may occur due to an incident light for some types of semiconductor chips.
It is an object of the present invention to provide a quality and reliable high-density package (CSP) semiconductor device without problems related to the manufacturing process.
In order to achieve the above object, the semiconductor device of the present invention is characterized by including:
a first semiconductor substrate piece having active elements and electrodes formed on its principal surface;
at least one semiconductor substrate mounting piece made of a same material as the first semiconductor substrate piece, the semiconductor substrate mounting piece being mounted on the principle surface side of the first semiconductor substrate piece, to be fitted within the principal surface,
wiring patterns including electrodes, formed on a surface of a semiconductor substrate mounting piece in a top layer of the semiconductor substrate mounting pieces;
external connection terminals formed on the wiring patterns; and
conductors for connecting the electrodes formed on the first semiconductor substrate piece and the electrodes formed on the semiconductor substrate mounting piece in the top layer.
According to the foregoing structure, the semiconductor substrate mounting piece in the top layer has the wiring patterns and external connection terminals formed on the surface thereof, which are electrically connected to the electrodes formed on the principal surface of the first semiconductor substrate piece, and the forgoing semiconductor substrate mounting piece in the top layer serves as an interposer.
Generally, for an interposer of a semiconductor device, resin-based (for example, polyimide, glass containing epoxy resin) insulating substrate is adopted. However, when adopting such resin insulating substrate as an interposer, fine wiring patterns are difficult to be formed, or a warpage of a wafer is likely to occur in the manufacturing process due to a difference in the linear thermal expansion coefficients between the insulating substrate and the semiconductor chip.
In contrast, according to the manufacturing method of the present invention, the semiconductor substrate mounting piece formed in the top layer as an interposer is made of a same material as the substrate (first semiconductor substrate piece) of the semiconductor chip. It is therefore possible to manufacture the semiconductor substrate mounting piece using the manufacturing line of semiconductor chips. As a result, fine wiring patterns can be formed. According to the structure of the present embodiment, it is also possible to form elements which could not be formed when adopting the conventional interposer made of a resin material. Furthermore, by adopting the semiconductor substrate mounting piece in the top layer made of a same material as the first semiconductor substrate, a difference in the linear thermal expansion coefficient between the first semiconductor substrate piece and the semiconductor substrate mounting piece in the top layer can be eliminated. It is therefore possible to eliminate the problem associated with a warpage of wafer due to heat applied in the manufacturing process.
Furthermore, since each mounting semiconductor substrate is arranged so as to be fitted within the size of the first semiconductor substrate piece obtained by dividing the first semiconductor substrate into pieces, such inconvenience associated with the conventional structure that conductors for connecting electrodes are provided outside the first semiconductor substrate piece can be eliminated. In the foregoing structure, the conductors may be arranged so as to connect the electrodes not only directly but also indirectly via other semiconductor substrate mounting piece.
As a result, the semiconductor device can be reduced in size to the first semiconductor substrate piece size, and in the meantime, a manufacturing cost can be reduced. Furthermore, problems related to the transportation due to a warpage of a wafer occurred in the manufacturing process, or related to the reliability in the connection by the conductors, or changes in quality due to applied heat can be prevented.